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CPU | High-performance 8051-compatible 8-bit CPU | 1 instruction = 1~3 machine cycle(s) | |||||
1 machine cycle = 4 clock cycles (typical) | |||||||
CPU operating clock can be configured: | Internal clock :7.5 MHz/15 MHz/30 MHz(nominal) | ||||||
External clock: Contact smart card input CLK supply via C3 (ISO/IEC 7816) | |||||||
Memories | FLASH | Size:132KB | |||||
Page size:512 bytes | |||||||
Erase and program operation: Page Erase, Byte Program and Consecutive Bytes Program | |||||||
Typical time: Erasing 2.5ms/page, Byte programming 37μs/byte, Consecutive bytes programming 5.6ms/page | |||||||
Bit logic: 1b after erasing, 0b after programming to be 0b | |||||||
Usage: code and data * Program can surmount the 64 KB limit, using CODE Banking * High 56 KB FLASH is accessible from XDATA | |||||||
RAM | Size: 2.25KB* 2048 bytes in XDATA * 256 bytes in IDATA | ||||||
OTP | User OTP:224bytes | ||||||
SN:17 bytes | |||||||
Algorithms and Peripherals | Symmetric algorithms | DES/T-DES | |||||
Peripherals | CRC: 16-bit CRC-CCITT | ||||||
TRNG: True Random Number Generator, for secure transactions | |||||||
Timer: One 16-bit timer, one ETU timer | |||||||
Interfaces | ISO/IEC 7816-3 serial interface | UART supporting ISO/IEC 7816-3 T=0/T=1 protocol and 11 baud rates: F/D = 11H, 12H, 13H, 18H, 91H, 92H, 93H, 94H, 95H, 96H, 97H | |||||
Support GSM power consumption standards, including Clock Stop mode | |||||||
Security | Scrambling data storage | ||||||
High/low voltage and high/low clock frequency detectors | |||||||
CLK filter(ISO/IEC 7816 external clock) | |||||||
Power glitch detectors | |||||||
Security Certification: EAL4+ | |||||||



















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