1.3.2. Processor Core
Dual-core ARM CortexTM-A7@1.2GHz
ARMv7 ISA standard ARM instruction set
Thumb-2 Technology
Jazeller RCT
NEON Advanced SIMD
VFPv4 floating point
Large Physical Address Extensions (LPAE)
Supports dynamic frequency scaling
32KB L1 Instruction cache and 32KB L1 Data cache per core
256KB L2 cache shared
1.3.3. Video Encoding Specifications
H.264 BP/MP/HP
H.265 MP
H.264/H.265 supports I/P frame, dual-P frame
MJPEG/JPEG baseline
1.3.4. Video Encoding Performance
Maximum 16-megapixel(4096x4096) resolution for H.264/H.265 encoding
Real-time multiple streams H.264/H.265 encoding capability:
3840 x 2160@30fps + VGA@30fps + 3840 x 2160@1fps snapshot
JPEG snapshot performance of 1080p@60fps independently
Supports the constant bit rate (CBR)/variable bit rate (VBR) bit rate control mode, ranging from 2kbit/s to 100Mbit/s
Encoding of eight regions of interest (ROIs)
Encoding frame rate ranging from 1/16 fps to 60 fps
1.3.5. Video Decoding Specifications
H.264 BP/MP/HP
H.265 MP
MJPEG/JPEG MP
1.3.6. Video Decoding Performance
H.264/H.265 decoding maximum resolution of 4096x4096
H.264/H.265 decoding maximum bit rate of 60Mbit/s
H.264/H.265 decoding performance of 4K@30fps
JPEG decoding performance of 1080p@100fps independently
1.3.7. Video and Graphics Processing
Lens distortion correction, fisheye (wall mounting/top mounting/bottom mounting) and PTZ calibration
Real-time stitch for two-channel images (panoramic 360°, wide angle 180°)
Picture rotation by 90°, 180° or 270°
Supports Electronic Image Stabilization Engine (EISE)
EISE: support frame rate up to 1080p@60fps
Supports 2 Video channels, up to 4K@30fps
Supports 2 UI channels, up to 1080p@60fps
Blending of 2 Video channels and 2 UI channels
Supports SmartColor for excellent display experience
1.3.8. ISP&VIPP
Supports 1 individual image signal processor (ISP), one supports 4224 x 3168 resolution
Adjustable 3A functions, including automatic exposure (AE), automatic white balance (AWB) and automatic focus (AF)
Highlight compensation, backlight compensation, gamma correction and color enhancement
Defect pixel correction, 2D/3D denoising
Sensor build-in WDR, 2F-line base WDR, local tone mapping
1/64 to 1x scaling output for 4 channels, among 2 channels supports frame buffer compress
On-screen display (OSD) overlay pre-processing for 8 regions and cover for 8 regions
Graphics mirror and flip
ISP tuning tools for the PC
Supports Dual Video Input Post Processor (VIPP), supports 4224 x 3168 resolution
Supports image interception
The output scaling of width is 1/8 ~ 1x
The output scaling of height is 1/8 ~ 1x
1.3.9. Security Engine
Encryption and decryption algorithms implemented by using hardware, including AES, DES and 3DES
Signature and verification algorithms implemented by using hardware, including RSA512/1024/2048/3072/4096bits
HASH tamper proofing algorithms implemented by using hardware, including MD5/SHA/HMAC
Hardware true random number generator (TRNG) and hardware pseudo random number generator (PRNG)
Integrated 2Kbits efuse storage space
sing hardware, including MD5/SHA/HMAC
1.3.10. Video Interface
1.3.10.1. Input
One combo sensors input
Main channel supports 4 lane mobile industry processor interface (MIPI), 12 lane sub low-voltage differential signaling
(sub-LVDS), and 4 lane high-speed serial pixel interface (HiSPI)
Compatibility with mainstream HD CMOS sensors provided by Sony, Aptina, Omni Vision and Panasonic
BT.601, BT.656 and BT.1120 video input interfaces
1.3.10.2. Output
One phase alternating line (PAL)/national television systems committee (NTSC) for automatic load detection
One BT.1120/BT.656 video output interface
One high definition multimedia interface (HDMI) output, up to 4K@30fps
One MIPI digital serial interface (DSI) output, up to 1920 x 1080@60fps
One RGB output
1.3.11. Audio Interfaces
Integrated audio codec, supporting 20-bit audio input and output
Inter-IC sound(I2S)/time division multiplex (TDM) interface for connecting to an external audio codec
Dual channel microphone differential input for reducing noise
1.3.12. Peripheral Interfaces
One internal RTC
Four channels general purpose analog-to-digital converter (GPADC)
6 UART interfaces
4 SPI interfaces
12-ch PWM Controller (CPUX:9, CPUS:3)
Three SD3.0/SDIO3.0 interfaces, supporting secure digital extended capacity (SDXC)
One USB2.0 OTG interface
RGMII in 10/100/1000 Mbit/s full-duplex or half-duplex mode, RMII in 10/100 Mbit/s full-duplex or half-duplex mode
Six TWI interfaces, one one-wire interface, one CIR RX interface, 126 GPIO interfaces
1.3.13. External Memory Interfaces
DDR3/DDR3L/LPDDR3/DDR4/LPDDR4 interface
- Supports 32/16-bit DDR3/DDR3L, up to 800MHz
- Supports 32/16-bit LPDDR3, up to 800MHz
- Supports 32/16-bit DDR4, up to 800MHz
- Supports 32/16-bit LPDDR4, up to 800MHz
SPI Nor Flash interface
- 1-, 2-, 4- wire mode
- 3 bytes or 4 bytes address mode
SPI Nand Flash interface
eMMC 5.0 interface
Nand Flash interface
- 8-bit data width
- 16-,24-,28-,32-,40-,44-,48-,52-,56-60-,64-,68-,72-,80-bit ECC
- SLC/MLC/TLC flash and EF-NAND memory
Booting from SPI NOR, SPI NAND, eMMC, SD, USB, UART or RAW NAND, one-key FEL
Hardware boot pin select
1.3.14. Physical Specifications
Power consumption
- TBD
- Multi-level power-saving mode
Operating voltages
- 0.9V core voltage
- 3.3V IO voltage
- 1.5V, 1.35V, 1.2V, 1.2V or 1.1V for DDR3/DDR3L/LPDDR3/DDR4/LPDDR4 interface
Package
- Restrictions on the use of certain hazardous substances (RoHS), thin & fine-pitch ball grid array (TFBGA)
- Body size of 14 mm x 14 mm, 0.5 mm ball pitch